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Milestones & Deliverables

Work Packages

 

 

The table below shows deliverables and milestones of WP4.

Click on the left-side number to get the summary report, when available.

No.

Deliverable : High Performance Computing

                   (HPC)

Lead Beneficiary Contributors

Milestones/Month

4.1

CTA-HPC: VHDL design + algorithm simulation study

UOXF, ULIV, ULEIC

18

4.2/4.3/4.4

CTA-HPC: FPGA based proto/test bench development

ULIV, UOXF, ULEIC, UvA

36/36

4.4

CTA-HPC: Tests results with Installation of a pathfinder at Meudon & results

ULIV, UOXF, ULEIC, UvA

48

4.5/4.6

PET-HPC: VHDL design/algorithms development

INFN, UC3M, PHILIPS

18/36

4.7/4.8

PET-HPC: FPGA-based tests bench prototype and results

INFN, UC3M, SEDECAL

36/48

 4.8 bis

PET-HPC: New processor based HPC test bench (Intel & others)

PHILIPS, TRT

36/48

4.9

HEP-HPC : VHDL Design & simulation

STFC, CERN, INFN, UBRIS, FNAL, CNRS

18

4.10

HEP-HPC : Proto design & construction

STFC, CERN, INFN, UBRIS, FNAL, CNRS

 

36

4.11

HEP-HPC : Demonstrator results

STFC, CERN, INFN, UBRIS, FNAL

48

4.12

HPC : Advanced digital processing architectures: Development of a new design tool for 3D based architecture

HPC: Advanced Heterogeneous architectures

CNRS- CEA LETI

 

 

   TRT

24

 

 

48

 

Deliverables are often written reports but can also take another form, for example the completion of a prototype etc. In such cases the deliverable are also documented in a written record of the achievement of the deliverable, including any available supporting material (e.g. photos of the prototype, the report of the conference….). 

 

Final Report

Find here the Final Report on WP4 in pdf format and in .docx format

 

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Read more, click here

Partners & Coordinators

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